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In every programming language there are sets of opcodes that are recommended over others. I've tried to list them here, in order of speed.

  1. Bitwise
  2. Integer Addition / Subtraction
  3. Integer Multiplication / Division
  4. Comparison
  5. Control flow
  6. Float Addition / Subtraction
  7. Float Multiplication / Division

Where you need high-performance code, C++ can be hand optimized in assembly, to use SIMD instructions or more efficient control flow, data types, etc. So I'm trying to understand if the data type (int32 / float32 / float64) or the operation used (*, +, &) affects performance at the CPU level.

  1. Is a single multiply slower on the CPU than an addition?
  2. In MCU theory you learn that speed of opcodes is determined by the number of CPU cycles it takes to execute. So does it mean that multiply takes 4 cycles and add takes 2?
  3. Exactly what are the speed characteristics of the basic math and control flow opcodes?
  4. If two opcodes take the same number of cycles to execute, then both can be used interchangeably without any performance gain / loss?
  5. Any other technical details you can share regarding x86 CPU performance is appreciated
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This sounds a lot like premature optimization, and remember that the compiler doesn't output what you type in, and you really don't want to write assembly unless you really really have too. –  Roy T. Apr 11 '12 at 10:02
Float multiplication and division are totally different things, you should not put them in the same category. For n-bit numbers, multiplication is a O(n) process, and division is a O(nlogn) process. This makes division about 5 times slower than multiplication on modern CPUs. –  sam hocevar Apr 11 '12 at 11:35
The only real answer is "profile it". –  Tetrad Apr 11 '12 at 17:00
Expanding on Roy's answer, hand optimizing assembly is almost always going to be a net loss unless you're really really exceptional. Modern CPUs are very complex beasts and good optimizing compilers pull off code transformations that are entirely non-obvious and not trivial to code by hand. Even for SSE/SIMD, always always use intrinsics in C/C++, and let the compiler optimize their usage for you. Using raw assembly disables compiler optimizations and you lose out big. –  Sean Middleditch Apr 11 '12 at 22:19
You don't need to hand-optimize to assembly to use SIMD. SIMD is very useful to optimize for depending on the situation, but there is a mostly-standard convention (it works on GCC and MSVC at least) for using SSE2. As far as your list is concerned, on a modern supserscalar multi-pipelined processor, data dependency and register pressure cause more issues than raw integer and sometimes floating point performance; the same is true of data locality. By the way, integer division is the same as multiplication on a modern x86 –  OrgnlDave Apr 12 '12 at 4:19

4 Answers 4

up vote 5 down vote accepted

Agner Fog's optimization guides are excellent. He has guides, tables of instruction timings, and docs on the microarchitecture of all recent x86 CPU designs (going back as far as Intel Pentium). See also some other resources linked from

Just for fun, I'll answer some of the questions (numbers from recent Intel CPUs). Choice of ops is not the major factor in optimizing code (unless you can avoid division.)

Is a single multiply slower on the CPU than an addition?

Yes (unless it's by a power of 2). (3-4x the latency, and uses more execution resources.) Don't go far out of your way to avoid it, though, since it's as fast as 2 or 3 adds.

Exactly what are the speed characteristics of the basic math and control flow opcodes?

See Agner Fog's instruction tables. Be careful with conditional jumps. Unconditional jumps (like function calls) have some small overhead, but not much.

If two opcodes take the same number of cycles to execute, then both can be used interchangeably without any performance gain / loss?

Nope, they might compete for the same execution port as something else, or they might not. It depends on what other dependency chains the CPU can be working on in parallel. (In practice, there's not usually any useful decision to be made. It occasionally comes up that you could use a vector shift or a vector shuffle, which run on different ports on Intel CPUs. But shift-by-bytes of the whole register (PSLLDQ etc.) runs in the shuffle unit.)

Any other technical details you can share regarding x86 CPU performance is appreciated

Agner Fog's microarch docs describe the pipelines of Intel and AMD CPUs in enough detail to work out exactly how many cycles a loop should take per iteration, and whether the bottleneck is uop throughput, a dependency chain, or contention for one execution port. See some of my answers on StackOverflow, like this one or this one.

Also, (and similar for earlier designs) is fun reading if you like CPU design.

Here's your list, sorted correctly for a Haswell CPU, based on my best guestimates. This isn't really a useful way of thinking about things for anything but tuning an asm loop, though. Cache / branch-prediction effects usually dominate, so write your code to have good patterns. Numbers are very hand-waivey, and try to account for high latency, even if throughput is not an issue, or for generating more uops which clog up the pipe for other things to happen in parallel. Esp. the cache / branch numbers are very made-up. Latency matters for loop-carried dependencies, throughput matters when each iteration is independent.

  • 1 Bitwise / Integer Addition / Subtraction /
    shift and rotate (compile-time const count) /
    vector versions of all of these vector shuffles. (1 to 4 per cycle throughput, 1 cycle latency)
  • 1 vector min, max, compare-equal (to create a mask)
  • 1.5 load / store (L1 cache hit)
  • 2 inserting general-purpose registers into vector elements (_mm_insert_epi8, etc.)
  • 2.5 shift / rotate by variable count (2c latency, one per 2c throughput)
  • 2.5 Comparison without branching (y = x ? a : b, or y = x >= 0) (test / setcc or cmov)
  • 3 Integer Multiplication, fp add/sub (and vector versions of the same) (1 or 2 per cycle throughtput, 3 to 5 cycle latency)
  • 3 int-> float conversion
  • 4 vector int compare-greater-than, vector int/fp mul
  • 4 predictable Control flow (predicted branch, call, return)
  • 5 vector horizontal ops (e.g. PHADD adding values within a vector)
  • 12? load/store (L3 cache hit)
  • 13? Control Flow (poorly-predicted branch)
  • 15 (vector)FP Division (10-13c latency, one per 7c throughput)
  • 17 int division (yes really, it's slower than FP division, and can't vectorize)
  • 17 (vector)FP sqrt
  • 20-25? Control Flow (predicted branch)
  • 50? FP trig / exp / log
  • 100? load/store (cache miss)
  • 3000??? read page from file (OS disk cache hit) (making up numbers here)
  • 20000??? disk read page (OS disk-cache miss, fast SSD) (totally made-up number)

The relative cost of things on AMD CPUs will be similar, except they have faster integer shifters when the shift-count is variable. AMD CPUs are of course slower on most code, for a variety of reasons.

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Great answer.... –  Geotarget Jul 26 at 7:24

It depends on the CPU in question, but for a modern CPU the list is something like this:

  1. Bitwise, addition, subtraction, comparison, multiplication
  2. Division
  3. Control flow (see answer 3)

Depending on CPU there may be a considerable toll for working with 64 bit data types.

Your questions:

  1. Not at all or not appreciably on a modern CPU. Depend on CPU.
  2. That information is something like 20 to 30 years outdated (School sucks, you have now got proof), modern CPUs handle a variable number of instructions per clock, how many depend on what the scheduler come up with.
  3. Division is a bit slower than the rest, control flow is very fast if the branch prediction is correct, and very slow if it is wrong (something like 20 cycles, depend on CPU). The result is that a lot of code is limited mainly by control flow. Don't do with an if what you can reasonably do with arithmetic.
  4. There is no fixed number for how many cycles any instruction take, but sometimes two different instructions may perform equally, put them in another context and maybe they don't, run them on a different CPU and you are likely to see a 3rd result.
  5. On top of control flow the other big time waster is cache misses, whenever you try to read data that is not in cache the CPU will have to wait for it to be fetched from memory. In general you should try to handle data pieces next to one another simultaneously rather than picking data out from all over the place.

And finally, if you are making a game, don't worry too much about all this, better concentrate on making a good game than chopping CPU cycles.

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I'd also like to point out that the FPU is pretty damn quick: especially on Intel - so fixed-point is only really needed if you want deterministic results. –  Jonathan Dickinson Apr 12 '12 at 11:03
I'd just put more emphasis on the last part - make a good game. It helps to have the code clear - which is why 3. only applies when you actually measure a performance problem. It's always easy to change those ifs into something better if the need arises. On the other hand, 5. is trickier - I definitely agree that that's a case where you really want to think first, since it usually means changing the architecture. –  Luaan Apr 30 '14 at 7:43

I made a test about integer operation witch looped a million times on x64_64 , reach brief conclusion like below,

add ---116 microseconds

sub----116 microseconds

mul----1036 microseconds

div----13037 microseconds

the data above have already reduced the overhead induced by loop,

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The intel processor manuals are a free download from their website. They are fairly large but technically can answer your question. The optimization manual in particular is what you are after, but the instruction manual also has the timings and latencies for most of the major CPU lines for simd instructions since they vary from chip to chip.

In general I would consider full branches as well as pointer-chasing (link list traverals, calling virtual functions) the top to perf killers, but the x86/x64 cpus are very good at both, compared to other architectures. If you ever port to another platform you will see how much of a problem they can be, if you are writing high performance code.

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